|ARM Technical Support Knowledge Articles|
You can hook up a PL192 Primecell VIC to the ARM core VIC port, then the VIC can supply the address for an IRQ ISR directly to the core which can significantly reduce interrupt latency (normally 1 or more branch instructions are required to get to the ISR address). Refer to the PL192 Technical Reference Manual for details on the VIC operation. Note that the CP15 c1 VE field needs to be set to ‘1’ to enable the VIC operation, otherwise the core will go to the vector table location (0x18 or 0xFFFF0018) for the IRQ information.
Article last edited on: 2008-09-09 15:47:51
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