|ARM Technical Support Knowledge Articles|
The functionality of the two stages is similar in the two cores.
In both cases the Issue stage is the last stage of the common pipeline and is responsible for passing the instruction to the correct second-stage pipeline (one of the ALU pipeline, Multiply pipeline or Load/Store pipeline in the ARM1136).
In the ARM1136, register reads (for retrieving operands) are performed in the issue stage.
In the ARM10 family of processors, there is more instruction decode logic performed in the issue stage; register reads and final instruction decoding are performed in the subsequent decode stage.
Article last edited on: 2008-09-09 15:47:51
Did you find this article helpful? Yes No
How can we improve this article?