|ARM Technical Support Knowledge Articles|
Applies to: ARM10 and ARM11 Cores
Any external abort which may be recognized at a point when the instruction that caused that access has retired, is considered an 'imprecise' abort (e.g. any external access except accesses to Strongly ordered memory, loads to the pc or cpsr, loads done in low-interrupt latency mode, or the load portion of a SWP instruction). These imprecise aborts are recognized only when the 'A' bit in the CPSR has been cleared. In general, it is not possible to determine the precise instruction which caused the abort and the OS will typically respond by killing the failing application.
Article last edited on: 2008-09-09 15:47:51
Did you find this article helpful? Yes No
How can we improve this article?