|ARM Technical Support Knowledge Articles|
Yes we have defined new memory types, Normal, Device, Strongly Ordered and also Shared memory. The idea is that is more useful to define the system behaviour in terms of a memory usage model, rather than just having the processor indicate whether an access is cachable or bufferable. For example some peripherals will require transactions to be done in order, so in that case a Strongly Ordered memory type can be used. Cachable accesses will use the Normal memory type. Device memory will be used for peripherals, this can be used to define which interface is used for a particular access (non shared Device memory accesses will be done on the peripheral interface on the ARM1136). Shared memory can be defined if memory is shared between different Masters on the AHB/AXI bus.
Article last edited on: 2008-09-09 15:47:51
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