|ARM Technical Support Knowledge Articles|
Low-latency mode has two effects:
- disables hit-under-miss;
- allows multi-access instructions (LDM/STM or unaligned loads and stores, to 'Normal' memory), to be abandoned part way through, when an interrupt is recognized. These instructions may then be restarted after the ISR.
The FI bit, bit 21, in CP15 register 1 enables a low interrupt latency configuration.
Note that for the ARM1176, the FI bit can only be modified in Secure state.
Article last edited on: 2008-09-09 15:47:51
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