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Applies to: GX175 Memory Controller
GX175 and most memory controllers in general only ensure that on the same AHB port, reads and writes are completed in the order they are sent. So, when an AHB master sends a write request to a memory location and then a read request to the same memory location, the write is completed first and then the read is serviced. However, write requests from multiple ports that write to the same memory location would not go through this check.
If at the system level it needs to be ensured that the data read back from one memory location is the data written to this location by another master, then this timing should be ensured at the system level. The memory controller will not take care of this. GX175 takes requests from its various AHB ports and services these requests in a performance efficient manner. This might entail servicing a read request from a higher priority port before a write request from a lower priority port. Hence it can not guarantee that access requests from different masters on different ports will get serviced in the order they are received.
Article last edited on: 2008-09-09 15:47:51
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