|ARM Technical Support Knowledge Articles|
The idea is to minimize the Page Table Walks, and more efficient use of TLB entries. For each 1MB section within the 16MB super section, the Page table descriptor must be the same, then when the core accesses an address within this 16MB region the translation table entry will be fetched into the TLB and the entry is tagged as a super section. Then subsequent accesses in that 16MB region will hit in the TLB and you will need 1 instead of 16 TLB entries to describe the translation information for the super section which minimizes TLB usage and Page Table walks.
Article last edited on: 2008-09-09 15:47:51
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