|ARM Technical Support Knowledge Articles|
The reason for using two pipeline stages for instruction fetch (and also two cycles for access to the data cache) is that it gives us time to convert a virtual address to a physical one, check for a hit in the cache, read the data back and do things like branch prediction with that data. If this all had to be done in a single cycle, rather than two, the maximum frequency of the processor would be much slower.
These two pipeline stages are not the only places where instructions are prefetched. Outside the integer core pipeline itself, there is a separate prefetch unit inside the core, which is described in detail in Chapter 5 of the ARM1136/1176 Technical Reference Manual. It fetches ahead of the integer core pipeline and performs dynamic branch prediction.
Article last edited on: 2008-09-09 15:47:51
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