|ARM Technical Support Knowledge Articles|
Yes, there are ports supplied on the ARM11 interfaces which could be used by a L2 Cache controller unit (L2CC) (e.g. the ARM L220 L2CC). You would hook up the ARSIDEBANDI/ARSDIDEBANDRW ports to the L220 if you wanted the L2 cache to exhibit inner cache attributes (i.e. the same as the core). You would hook up the ARCACHEI/ARCACHERW ports to the L220 if you wanted the L2 cache to exhibit outer cache attributes. Other AXI data/instruction port signals like AWPROTRW/I or WSTRBRW/I etc. can also be used by the L220 to monitor transactions from the core.
Article last edited on: 2008-09-09 15:47:51
Did you find this article helpful? Yes No
How can we improve this article?