|ARM Technical Support Knowledge Articles|
When debugging using RVD/RVI, certain events can cause the data cache to be cleaned and invalidated, or the instruction cache to be invalidated. In general, using software breakpoints, high-level single stepping or accessing cacheable regions of memory during debug will have some effect on the caches.
While this does not directly affect the correct operation of your code, it will have an impact on measurements of real-time performance (benchmarks). RVI does not attempt to preserve the contents of the caches during debug, but will always maintain coherency between the caches and main memory.
Note that RVD/RVI only support level 1 ARM caches. Level 2 and proprietary caches on a specific SoC or MCU are not supported. If these are present then coherency could be lost. If the L2 cache is unified then coherency will generally be maintained, otherwise the L2 cache should be manually disabled.
Article last edited on: 2009-02-23 10:06:53
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