ARM Technical Support Knowledge Articles

How do RVI and MultiICE access memory on a hardware target?

Applies to: Multi-ICE, RealView Development Suite (RVDS), RealView ICE and Trace (RVI / RVT)


The debugger cannot access target memory directly (on pre CoreSight memory systems).

Accesses to memory (such as image load or debugger memory pane updates) are performed by scanning standard ARM load and store instructions into the core (using the JTAG clock) and executing them at full system speed. This ensures that timing requirements for memory accesses are met.

For example, when the debugger requests a memory read from address 0x10000 (4 words), this will translate into the following basic steps:

1. MOV and LDR instructions are scanned into the ARM core and executed to read the desired words from external memory into registers.

MOV r0, #0x10000
LDM r0, {r5-r8} 

2. A STM is then used to return the values. During this phase the core is isolated from the memory bus and the values written are retrieved over JTAG.

MOV r0, #0x0    ; Dummy value. Core is isolated so will not actually
                ; access this memory
STM r0, {r5-r8}

Article last edited on: 2008-09-09 15:47:52

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