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Applies to: PL340 AXI SDRAM Controller
The constraints on PL340 are set such that the paths are all correctly constrained whether aclk and mclk are in sync or not. This is achieved by simultaneously defining a sync clock and an async clock constraints on the aclk port. False paths are then set between the async aclk and sync clock domains so that these paths are only constrained by the sync constraints. Therefore there is no need to remove the false paths if aclk is in sync with mclk since the relevant constraints are always set on the clocks in the PL340 synthesis scripts.
Article last edited on: 2008-09-09 15:47:52
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