ARM Technical Support Knowledge Articles

Is it enough for the system clock controller to only monitor csysack of PL340 to know whether PL340 has acknowledged the low power request on csysreq?

Applies to: PL340 AXI SDRAM Controller


Yes. cactive will always go low before csysack is asserted, so it is enough to only monitor csysack in this case.

Article last edited on: 2008-09-09 15:47:52

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