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Applies to: PL340 AXI SDRAM Controller
The ap bit is output on address bit 10 or 8 depending on how it is programmed. It is also output on the ap signal. This is done so that when an EBI is used the ap bit can bypass the EBI mux and replace a8 or 10 before the memory device for PL340 only. This then enables the PL340 to be auto refreshed whilst the EBI has granted the memory add and data busses to another memory controller. If an EBI is not used then the AP bit can be left not connected. Please see section 2.5 in the PL340 integration Manual for more information.
Article last edited on: 2008-09-09 15:47:52
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