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Applies to: PL351 NAND Flash Memory Controller
PL351 doesn't support commands that do not incur a busy period between command and data phased during NAND booting. This is because the controller must inspect busy before commencing the read data access. PL351 is designed to begin the data access following a rising edge of the busy signal. Any other solution would require a configurable parameter to set the delay before inspecting the state of the busy signal.
A suggested workaround would be to issue an initial PAGE READ command with nand_booten asserted and perform an initial data access, then de-assert nand_booten and perform any RANDOM DATA OUT commands to the same page. The NAND boot logic external to PL351 would need to retain knowledge of previous transactions in order to determine which command to use.
Article last edited on: 2008-11-05 08:34:29
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