ARM Technical Support Knowledge Articles

When using a synchronous clocking strategy the int_n and busy_n inputs have paths into the aclk domain. If a large delay is placed on the mclk signals these paths become untenable at high ACLK frequencies. Any workaround for this problem?

Applies to: PL350 AXI Static Memory Controller

Answer

In the case where the delay of the busy line means that it cannot be captured in a synchronous fashion within the PL350, then essentially this signal becomes asynchronous. Therefore the busy line can be synchronized using two registers to ensure that when the PL350 does see the signal it is really synced up. These additional registers do not require to be inside the PL350. They can be added between the busy IO pad and the PL350.

Article last edited on: 2008-11-05 08:23:18

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