ARM Technical Support Knowledge Articles

How fast is the EB?

Applies to: EB (Emulation Baseboard)

Answer

[updated 18 September 2007]

Our development boards enable you to prototype hardware and software with ARM cores. Please note that the Emulation Baseboard (EB) is based on an FPGA, so that you can use a wide range of test chips on Core Tiles, and as such is much slower than the SoC in your final product. If you need a faster board then you should use a Platform Baseboard, which has near SoC performance.

The table below shows typical performance for burst transfers on the EB, with throughput measured in Mbyte/second. The types of memory listed on the left of the table are SDRAM and SSRAM on the baseboard, SSRAM on the Logic Tile (LT), PCI memory space accesses to SDRAM on the baseboard, and DMA from SDRAM to SDRAM. Table entries with three figures are respectively: instruction fetch / data read / data write. For example, the CT11MPCore can burst write to the EB's SDRAM at 8M byte/second.

 AHB bus

 EB with AHB bus

 EB with AXI bus

 

 PB926EJ-S

 CT7TDMI

 CT926EJ-S

 CT1136JF-S

 CT1156T2F-S

 CT11MPCore

 SDRAM

109 / 100 / 148

5 / 4 / 6

6 / 5 / 7

5 / 4 / 5

34 / 33 / 44

27 / 21 / 8

 SSRAM

26 / 25 / 44

6 / 5 / 6

7 / 6 / 9

6 / 5 / 8

8 / 8 / 11

8 / 8 / 7

 LT SSRAM

56 / 57 / 56

76 / 24 / 24

19 / 14 / 12

12 / 9 / 8

55 / 25 / 59

46 / 17 / 6

 PCI memory

5 / 4 / 13

0.6 / 0.6 / 6

0.6 / 0.6 / 6

0.4 / 0.4 / 6

0.5 / 0.5 / 6

0.6 / 0.6 / 7

 DMA

33

4

5

7

10

11

Test conditions:

  • L1 instruction cache is enabled, other L1/L2 caches are disabled. CT7TDMI has no caches.
  • Color LCD Controller is disabled.
  • The data read and data write figures were measured using load multiple (LDM) and store multiple (STM) instructions running from SDRAM.
  • CT11MPCore + EB was measured using AN152 FPGA build C7; the PCI figures used build C6.
  • Clock frequencies are listed below for comparison. ARM core frequency has very little effect.

The clock frequencies for the different platforms are:

  • PB926 has 70MHz SDRAM and SSRAM; external buses to PCI and Logic Tile SSRAM are 35MHz.
  • EB has 30MHz bus to Core Tile, DDR SDRAM, SSRAM and bus to PCI; Logic Tile SSRAM is 25MHz.
  • EB with CT7TDMI all runs at 20MHz.

Slow throughput for the CT926 and CT1136 is due to limitations in test chip implementation:

  • The ARM926EJ-S core has Harvard architecture with separate data and instruction buses, but the test chip is limited by the number of pins to a single AHB interface. An arbiter within the test chip assigns a higher priority to the data bus. When the processor accesses the data bus during a fixed length burst on the instruction bus, the instruction bus is de-granted in favour of the data bus. This produces incomplete fixed length bursts on the test chip's AHB interface. Early burst termination is not supported by the AXI bus infrastructure so the burst information is removed in the AHB-AXI bridge in the EB FPGA, resulting in single accesses.

  • The ARM1136JF-S test chip generates the following AHB accesses for a burst: NonSeq - Busy - Seq - Busy - Seq - Busy. Unfortunately the PL340 memory controller used in the EB FPGA does not respond efficiently to this type of burst, which results in the same wait states as if the processor was generating single accesses.

If you want more details then you can run our memory performance program on the EB yourself. We do not provide complex latency information for the many EB designs; although we do provide timing information for the PB926 in our FAQ: How fast is Versatile/PB926EJ-S? .

Attachments: memperf.zip

Article last edited on: 2009-01-20 16:29:22

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