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Applies to: RealView ICE and Trace (RVI / RVT)
RealView Trace can officially sample the ETM trace port at a maximum frequency of up to 250MHz.
For ETM architecture V1 and V2 implementations (eg: non CoreSight ARM7 and ARM9 designs) the trace port clock is equivalent to the core clock - hence a 250 MHz trace clock equates to a 250MHz core clock.
Double Data Rate (DDR), or half rate clocking, is a configurable ETM feature which allows the trace port frequency to be halved, but still convey the same amount of trace sample data. This is achieved by changing the trace port signals on both the rising edge, and falling edge of the trace port clock. When using this configuration, the RealView-Trace maximum operating frequency is halved – so a 125MHz max trace port clock is supported.
For ETM architecture V3 implementations (eg: ARM11 and CoreSight designs) the trace port clock can be an integer divisor of the core clock (/4, /8) or asynchronous to the core clock. This is possible because the trace output is packetised. ETM architecture v3 and later use DDR clocking by default.
RealView Trace can trace a core running up to 1 GHz core clock frequency with an architecture V3 ETM.
This is based on a core clock / 8, trace port clock configuration and equates to a 125MHz double data rate trace clock. Note: The slower the trace port clock, the more likely you are to get ETM FIFO overflows, especially if you have a small trace port (4 or 8 pins), and are tracing data. A FIFO will either stall the processor or result in a loss of trace information.
Please see the Embedded Trace Macrocell Architecture Specification for more information on the Embedded Trace Macrocell (ETM).
Article last edited on: 2008-09-09 15:47:53
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