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Applies to: LT-XC4V (Virtex-4)
[Updated 21 Sep 2009]
The diagram attached to this article shows FPGA I/O connections for the Virtex-4 Logic Tile. The FPGA banks are shared between upper headers (XU, YU, ZU, Z) for communication with a top Logic Tile or daughter card, and lower headers (XL, YL, ZL, Z) for communication with a baseboard or bottom Logic Tile.
The I/O communication between FPGAs in a stack of Logic Tiles is significantly increased using configurable switches (upper fold, lower fold, thru):
Article last edited on: 2009-09-22 15:07:57
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