|ARM Technical Support Knowledge Articles|
Applies to: LT-XC4V (Virtex-4)
[new 4 October 2007]
We provide example designs for AHB and AXI peripherals implemented in Logic Tiles, and recommend customers use these as starting points for their own projects. This will help prevent board damage by erroneous pin assignment and facilitates technical support. The example designs include a pin constraints file and RTL for a bus master and slave.
Article last edited on: 2009-01-20 15:33:01
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