|ARM Technical Support Knowledge Articles|
Unlike traditional ARM based JTAG designs, where cores are directly accessible through the TAP on the scan chain, CoreSight system components are accessed by specifying a DAP Access Port (AP) and address. The following FAQ discusses how to configure RVI to debug your CoreSight system. It assumes users have at least: RVDS/RVD v3.1.
Connect RVI’s JTAG cable to your targets JTAG connector.
Power up your board and the RVI.
Start RVD and navigate to the Connect to Target window.
In the Connect to Target window, expand the RealView ICE option in the window, right-click on one of your current configurations, and select Configure…. This should bring up the RVConfig window.
In the RVConfig window, connect to your RVI.
Click the Auto Configure Scan Chain button. This should insert an ARMCS-DP (DAP) into the RVConfig window.
Right-click on the ARMCS-DP component and select Read CoreSight ROM table. This should cause the core and the other CoreSight components in your system to appear in the RVConfig window.
If reading the ROM table does not cause your core and CoreSight components to be included in the RVConfig window, you will need to manually add the missing components using the Add Device… button. Because these components are behind a DAP, it does not matter which order you add your components.
Verify that each component in the RVConfig window contains the correct CoreSight AP index and CoreSight base address by clicking on the appropriate component in the left-hand panel of the RVConfig window.
The CoreSight AP index refers to the index of the AP inside the DAP your component is connected to. The CoreSight base address refers to the starting address of the debug registers for your component.
Save and exit the RVConfig window.
In the Connect to Target window, you should see your CoreSight components listed under the RealView ICE connection.
Double click on the ARM core to connect and debug. Registers associated with other CoreSight components (eg: ETM, TPIU, etc) can be configured by connecting to the relevant component and opening the RVD register window.
The above screenshots are provided as an example configuration for a simple Cortex-R4 based CoreSight system. ** Please note: the actual settings may differ from your hardware **
Article last edited on: 2008-09-09 15:47:56
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