|ARM Technical Support Knowledge Articles|
[new 20 November 2007]
Application Note AN119 is an essential first step for checking your Virtex-II Logic Tile works with other boards in your system. It should also be used as a starting point for custom logic designs. This FAQ should help you with some common problems. See AN119 section 2 'Getting Started' for other set-up details.
There are 3 common problems:
Which Progcards option should I use?
When you run Progcards from an AN119 boardfiles directory, it detects which Logic Tile (LT-XC2V6000 or LT-XC2V8000) is in your system, but not which other boards, so it offers you some confusing choices:
Several possible boards detected at TAP position 6:-
0: Quit progcards
1: AN119 (DEFAULT) for Integrator -> flash (addr 0x400000) Rev B Build 2
2: AN119 for CM + IM-LT1 + LT -> flash (addr 0x400000) Rev B Build 2
3: AN119 for CM with Masters CM + IM-LT1 + LT -> flash (addr 0x400000) Rev B Build 2
4: AN119 for Integrator with Masters -> flash (addr 0x400000) Rev B Build 2
5: AN119 for PB926 with Masters (Async clocks) -> flash (addr 0x400000) Rev D Build 2
6: AN119 for PB926 with Masters (Sync clocks) -> flash (addr 0x400000) Rev D Build 2
7: Logic Tile (skip)
8: Logic Tile LT-XC2V6000/LT-XC2V8000 (HPI-0102CD) bytestreamer build 3
Select option 0 (quit) if you do not want to program the Logic Tile. Select option 7 (skip) if you want to program other devices in the system. Do not select option 8 (bytestreamer) unless you need to reprogram the Logic Tile PLD.
Please note that the number of menu items and the way the numbers relate to the items may change, depending on how many .brd files Progcards finds in its execution directory.
To interpret the other options look for these keywords in the title:
So for Integrator systems:
|AN119 (DEFAULT) for Integrator||AP/CP + CM + IM-LT1 + LT|
|AN119 for CM + IM-LT1 + LT||CM + IM-LT1 + LT|
|AN119 for CM with Masters CM + IM-LT1 + LT||CM + IM-LT1 + LT|
|AN119 for Integrator with Masters||AP + CM + IM-LT1 + LT|
For Versatile PB926 systems, "async" and "sync" refers to the Logic Tile clock source. The design in the Logic Tile's FPGA can be synchronous to the Dev Chip internal AHB bus, with a default external AHB bus frequency of 35MHz. If your logic is not fast enough you can use PB926 switch S1-5 ON to reduce the external bus to 10MHz. Note this also reduces the CPU to 60MHz and internal bus to 20MHz. If reducing the bus clock improves operation, you can then try adjusting the programmable clock oscillator OSC0 upwards to find the maximum operating frequency. An alternative solution is to run the Logic Tile design asynchronous to the ARM core. Set PB926 switch S1-3 OFF for sync mode, or ON for async mode.
Unfortunately the AN119 FPGA image for PB926 has borderline timing for some LT-XC2V8000 Logic Tiles. Usually the Logic Tile SSRAM test fails. If this happens then you should use async mode.
Which test software should I use?
The AN119 test software directories are named consistent with the above. For clarity:
|coremodule||CM + IM-LT1 + LT|
|integrator||AP/CP + CM + IM-LT1 + LT|
|master_coremodule||CM + IM-LT1 + LT|
|master_integrator||AP + CM + IM-LT1 + LT|
|master_pb926ejs||PB926 + LT|
Which Logic Tile switch settings should I use?
Most of our Progcards .brd files use Logic Tile image 0, but those provided with AN119 use image 1. You can tell this if you look in the .brd file and see lines like this:
Step2Method = IntelFlash
Step2Address = 400000
If the address is zero or not present then it uses image 0: set switches S2-1 OFF and S2-2 OFF.
If the address is non-zero then it uses image 1: set switches S2-1 OFF and S2-2 ON.
Article last edited on: 2009-01-20 16:02:48
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