ARM Technical Support Knowledge Articles

How many clock cycles should the reset signal in an AMBA system be asserted for?

Applies to: AHB, APB


It is recommended that master and slave components should clearly state if they have a reset requirement greater than 1 or 2 cycles. It is also recommended that the system design should hold reset asserted for at least 16 cycles, unless it is known that a master or slave component has a longer reset requirement.

Article last edited on: 2008-09-09 15:47:56

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