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Applies to: AHB
An AHB-lite system does not have any arbitration logic, so the full AHB master will be permanently granted. The full AHB master HBUSREQ output will be left unconnected, and the HGRANT input tied to logic '1' (1'b1).
As AHB-lite does not support SPLIT or RETRY responses, the AHB-lite HRESP signal is a single bit, so the full AHB master HRESP[1:0] input should have HRESP tied to logic '0' (1'b0).
The full AHB master drives HLOCK in advance of the LOCKed transfer address phase, and this would normally be retimed in full AHB by an Arbiter module to produce HMASTLOCK, which is address phase aligned.
The following Verilog code would implement the required AHB HLOCK -> AHB-lite HMASTLOCK retiming function.
always @( negedge (HRESETn) or posedge (HCLK) )
HMASTLOCK <= 1'b0;
HMASTLOCK <= HLOCK;
Article last edited on: 2008-09-09 15:47:56
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