|ARM Technical Support Knowledge Articles|
Applies to: EB (Emulation Baseboard)
[new 20 November 2007]
Some Evaluation Baseboard (EB) users may encounter some difficulty in programming the configuration flash for the system FPGA when using RealView ICE (RVI).
This is due to signal integrity on the EB when using the short parallel cable from the RVI unit when connecting to the EB.
This can affect both RevC and RevD boards.
The following list shows available workarounds if a problem is encountered when trying to program the configuration flash
Article last edited on: 2009-01-20 18:19:08
Did you find this article helpful? Yes No
How can we improve this article?