|ARM Technical Support Knowledge Articles|
This FAQ is applicable when running a CT1176JZF-S on an Emulation Baseboard with the FPGA images provided with AN177.
Firstly, ensure that you have connected the trace probe to the TRACEA connector on the Core Tile. The Mictor Trace connectors on the EB do not allow access to the core ETM.
In this configuration the ARM1176JZF-S on the Core Tile runs at 360MHz by default, which is currently too fast for RealView Profiler. You will need to slow down the clock to 250MHz or less to perform hardware profiling. To do this you can use the clock test application from the Versatile CD - this is located at
The core clock frequency is calculated as:
Core Frequency = ( (REFCLK / indiv) * (vcodiv / 2outdiv + 1) ) / clkdiv
indiv = PLL input divider
vcodiv = VCO Output divider
outdiv = PLL output divider
clkdiv = Core clk divider
For more information refer to AN177 and the technical reference manuals for the EB and the CT1176JZF-S.
For example, to clock the core down to 200MHz, enter the following values when prompted:
PLL input divider 1
PLL VCO divider 80
PLL output divider 2
Core clk divider 0
Internal clk divider 1
External clk divider 3
You will then need to reset the board with no debugger attached.
Article last edited on: 2011-09-12 17:09:42
Did you find this article helpful? Yes No
How can we improve this article?