ARM Technical Support Knowledge Articles

Is it possible to configure the cache sizes and memory timings on the RTSMs?

Applies to: RealView Development Suite (RVDS)

Answer

No – the RTSMs (Real Time System Models produced by System Generator) do not model the effects of caches or memory latencies. These functionally accurate models use code translation technology to achieve high simulation speeds, and so do not have a concept of memory latency.
It is possible to alter relative clocking rates between System Generator components, however this will affect event timing within the system rather than cycle counts.

 

Article last edited on: 2011-08-17 17:54:26

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