ARM Technical Support Knowledge Articles

Why do I see "Error: invalid absolute file" when I debug my CEVA DSP?

Applies to: RealView Development Suite (RVDS)


RVD support for CEVA DSPs was tested using images built with CEVA SmartNcode Software Development Tools v9.0. Later versions of these tools are not officially supported by RVD.  Attempting to debug an image built with later versions of the tools may produce errors of the form:

      Error: invalid absolute file: Bad .scl(xx) Sym func_start_@@@_label(yy)

These errors should not prevent the image from loading, but they may prevent high level debug in the affected areas.

For additional information on RVD support for CEVA DSPs please see the FAQ "Do RVD and RVI support CEVA digital signal processors". 

Article last edited on: 2008-09-09 15:47:57

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