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Why does the Cortex-M3 TRM imply that Cortex-M3 can fetch from Peripheral and External Device memory?

Applies to: Cortex-M3

Answer

Table 4-1 of the Cortex-M3 Technical Reference Manual (ARM DDI 0337) is correct because the MPU can override the default memory properties of these regions shown in Table 4-2. (There is also a semantic argument about whether a 'fetch' takes place to an 'XN' region in any case, as the 'XN' will not prevent the I-side read from the memory, but will only prevent the eventual execution of the resulting opcode.)

Table 4-2 represents the attributes of the default memory map. The MMU can override most of these attributes, which is not stated explicitly, but can be inferred from the Note below the table, specifying which of the attributes (XN on PPB and System space) may NOT be overridden by the MPU.

--- Note ---
Private Peripheral Bus and System space at 0xE0000000 - 0xFFFFFFFF are permanently XN. The MPU cannot change this.
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