ARM Technical Support Knowledge Articles

What is the gate-count of the PL310 (AXI Level 2 Cache Controller)

Applies to: AXI PL310 L2CC



Gates Comments
1s1m 110 kgates  
2s1m 153 kgates impact of 1 slave ~ 43 kgates
2s2m 175 kgates 1 master port ~ 22 kgates
2s2m 16 ways 180 kgates 16 way implementation ~ 5 kgates compared to 8 ways
2s2m parity 186 kgates parity ~ 11 kgates (without taking into account the impact in the RAM array, cf. Data parity RAM one additional bit in Tag RAM)
2s2m address filtering 180 kgates address filtering ~ 5 kgates
2s2m lockdown by line 176 kgates 1 kgate (without taking into account the impact on the Tag RAM, ie. one additional bit)
2s2m lockdown by master ID 179 kgates lockdown by master ID ~ 4 kgates

With the same assumptions and flow, the L220 r1p7 2s2m synthesizes to 89 kgates. However, this must be compared to PL310 1s1m, as PL310 1s1m is still (much) more powerful than L220 2s2m in terms of performance.

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