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Is it possible to not have arbitration if there is only one slave interface on the PL301?

Scenario

1)

Is it possible to not have arbitration (or at least not use a cycle for arbitration) if there is only one slave interface on a fabric?

Let's say you have this fabric: 1 slave interface, 2 master interfaces (a 1:2 fabric).

It would seem like there would be no need for an arbiter for either master interface.  If this is true, and given the small size of the fabric, there would be a good case no regslices would be needed either.

2)

Assuming no regslices (or decode registers), could this fabric configuration essentially be a flow-though fabric, or are there registers somewhere?

If there is a register stage, which signals get registered, and where?

3)

Does the arbitration block add a wasteful cycle of latency - even though it really isn't needed?

Answer

1) Yes.  Arbitration is removed at each master interface that is only connected to one slave interface.  In your above example, the arbitration at each MI is removed because each MI is connected only to SI0 (the only master).

For this, refer to the PL301 Technical Summary in section 3.3 "Arbitration control":

"When a master interface has connections to only one slave interface its operation is much simpler and as a result the arbitration mechanism is removed. If you attempt to configure or interrogate the arbitration mechanism for such a master interface, all writes will be ignored, and each read will return all zeroes."

You can also compare a 1x2 PL301 with a 2x2 PL301 and find:

Axibm_master_int_arb_a_PL301xxxxx.v is empty for a 1x2 configuration, whereas this file does hold arbitration logic for a 2x2 configuration.

2) Since there are multiple slaves in this case (a 1x1 PL301 is not a valid configuration), there will be arbitration logic at each SI, so that the SI is aware of which MI it is handshaking with.  This is with respect to the read response (R-channel) and write response (B-channel) signals. Additionally, there will always be a 1 clock cycle latency each time the slave interface arbiter switches slaves.

You can also see that in file "axibm_slave_int_w_fifo_PL301xxxxx.v", AWVALID and AWREADY are registered at the slave interface. This module stores the slave numbers of outstanding transactions in order to meet the ordering constraints.

  3) No, as discussed above.

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