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I have a scenario where read access to a classical DDR memory is made via chip select 1.
Read access to NVM-DDR on chip select 0 and write accesses to DDR on chip select 1 work fine but the first read access to the DDR via chip select 1 fails. The related denali error message is:
# *Denali* Error: </alv_tb_chip/a_extmem_subsys/memory_cs1_e1/a_ddr_4/memory>@1489165810 ps :: Bank 0 must be in the active state before accepting command 'Read'. Bank 0 is in the Idle state.
For the read command to DDR on chip select 1, I realized that there is no 'activate' command preceeding the read command. I would expect an initial 'normal' read operation sequence to be be preceeded by an 'activate' command.
This could possibly be a clock syncronization issue. First, check that an activate command is in fact being attempted by the PL340. You should check the following input signals to module pl340_padif_PL340r3_xxx_xxxx.v:
Command_cs_n = CSx
Command_ras_n = 0
Command_cas_n = 1
Command_we_n = 1
If the above signals are set correctly, then check the outputs of this same module:
Cs_n = ?
Ras_n = ?
Cas_n = ?
We_n = ?
The following code block controls whether the inputs to this module reach the outputs correctly.
Always @ (posedge mclkn or negedge mresetn_n)
ras_n <= command_ras_n
cas_n <= command_cas_n
we_n <= command_we_n
cs_n <= command_cs_n
If they are not correctly reaching the outputs, then check whether you have set the clock synchronization bits correctly in the memory_cfg2 register:
Bit 1: a_gt_m_sync - Requires to be set HIGH when running the aclk and mclk synchronously but with aclk running faster than mclk.
Bit 0: Set high when aclk and mclk are synchronous.Looking at the waveforms, it looks like you've only set bit 0.
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