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Does the Pl340N support burst terminate commands (as described on most SDRAM data sheets)? If not, how does the PL340N stop the transmission of a burst in progress?
The PL340 supports burst termination on reads. For writes, it supports burst termination on the same chip-select with a command, for example a read/write/precharge command for the same chip-select.
Reads can be terminated by the following commands to the same CS:
Writes can be terminated by the following commands to the same CS:
Furthermore, read burst termination within the PL340 is automatic - a memory read burst will always be terminated if the read access is less than the programmed memory burst length. Whether the terminating command for that read access is another read, a BST or a precharge is dependant on the next arbitrated memory command and whether it can legally terminate the read or not.
If a write burst access is less than the programmed memory burst length, and there are no other outstanding commands, the PL340 can deassert dqs for the remaining beats of the memory burst (of programmed length), indicating there is no valid data on the bus.
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