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How do the synchronization primitives work in coherent regions of an MPCore processor

Applies to: Processor Cores


In uncached regions, a global exclusive monitor ensures correct operation of synchronization primitives LDREX/STREX.

In cached regions, a local exclusive monitor fills the same function for the executing processor only - no external synchronization will take place.

How is this resolved in coherent regions, managed by the Snoop Control Unit in MPCore systems?


There are two steps to this:

1: The Snoop Control Unit allows a cache line accessed by an LDREX instruction to exist in only one L1 data cache in the MPCore - in MESI Modified state.

2: Because of this, the local exclusive monitor can still be used, just as if the variable was located in a non-coherent cacheable region.

When a line containing the variable guarded by the local exclusive monitor gets migrated to a different processor's L1 data cache, this migration will in itself cause the monitor to be reset into open state.

One side effect of this is that the smallest size that can be monitored by an exclusive operation is a full cache line (8 words in both ARM11 MPCore and Cortex-A9 MPCore). This can potentially lead to "false negatives", forcing processors to retry semaphore operations which should "logically" have been able to complete in parallel - if they reside in the same cache line. As a result, if your multithreaded application contains multiple frequently accessed semaphores, it may be good for performance to ensure that they are located at least 8 words apart in memory.

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