ARM Technical Support Knowledge Articles

Are the PL011 UART and APB clocks synchronous?

Applies to: PL011 UART

Scenario

I'd like to know whether the PL011 UART clock, UARTCLK, and the APB clock, PCLK, have to be synchronous or not.

Answer

PL011 UART supports both asynchronous and synchronous operation of the
clocks. Internal synchronizers ensure synchronization between signals
crossing to and from the UARTCLK and PCLK domains.

Quote from UART Technical Reference Manual:

"The UART supports both asynchronous and synchronous operation of the
clocks, PCLK and UARTCLK. Synchronization registers and handshaking logic have
been implemented, and are active at all times. This has a minimal impact on
performance or area. Synchronization of control signals is performed on both directions
of data flow, that is from the PCLK to the UARTCLK domain, and from the UARTCLK to the
PCLK domain."

The limit to the frequencies of the UARTCLK and PCLK is given by the
formula:

	FUARTCLK <= 5/3 x FPCLK

Again, this is explained in the TRM:

"The frequency selected for UARTCLK must accommodate the desired range
of baud rates:

FUARTCLK (min) >= 16 x baud_rate (max)
FUARTCLK(max) <= 16 x 65535 x baud_rate (min)

For example, for a range of baud rates from 110 baud to 460800 baud the
UARTCLK frequency must be within the range 7.3728MHz to 115MHz.

The frequency of UARTCLK must also be within the required error limits
for all baud rates to be used.

There is also a constraint on the ratio of clock frequencies for PCLK to
UARTCLK. The frequency of UARTCLK must be no more than 5/3 times faster than the
frequency of PCLK:

FUARTCLK <= 5/3 x FPCLK

This allows sufficient time to write the received data to the receive
FIFO."

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