Can the ARM compiler workaround Cortex-M3 erratum 602117 ?

Applies to: DS-5, RealView Development Suite (RVDS)

Scenario

Use of an LDRD instruction, where the base register is also the first loaded register, can result in the corruption of the base register in certain circumstances, as described in Cortex-M3 erratum 602117.

Answer

RVCT 4.1 and ARM Compiler 5 do not generate LDRD instructions with the problematic register combinations.  The C/C++ libraries also avoid these instructions.  Compiler patches for RVCT 3.1 and RVCT 4.0 are also available which avoid this issue.

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Submit Rating and Feedback