|ARM Technical Support Knowledge Articles|
Use of an
LDRD instruction, where the base register is also the first loaded register, can result in the corruption of the base register in certain circumstances, as described in Cortex-M3 erratum 602117.
RVCT 4.1 and ARM Compiler 5 do not generate
LDRD instructions with the problematic register combinations. The C/C++ libraries also avoid these instructions. Compiler patches for RVCT 3.1 and RVCT 4.0 are also available which avoid this issue.
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