|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M3
Example code has a mixture of 16 and 32-bit opcodes as follows: 0x8000 16-bit 0x8002 32-bit 0x8006 16-bit 0x8008 16-bit 0x800a 32-bit ...
Cortex-M3 has a 3-word prefetch buffer, and always reads a 32-bit aligned word into the buffer if there is space in the buffer. When the processor branches to the example code, the behaviour will be: Cycle 1: fetch the instruction at 8000 and the first half of the instruciton at 8002 Cycle 2: decode the first instruction and fetch the second half of the instruction at 8002 and the instruction at 8006 Cycle 3: execute the first instruction, decode the second instruction, and fetch the instruction at 8008 and the first half of the instruction at 800a and so on. The 'fetch' is decoupled from the 'decode', so the 'fetch' does not need to know about which opcodes are 16 bit and which opcodes are 32-bit. The 'decode' stage of the pipeline takes care of working out which bytes in the buffer are needed to make up a whole opcode.
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