|ARM Technical Support Knowledge Articles|
Applies to: Debug and Trace
The SoC should be identified by a unique part number and revision number encoded in the CoreSight ROM table. If a SoC contains more than one top level ROM table, the SoC should be uniquely identified by the combination of the IDs of the individual top level ROM tables. The registers for identifying the SoC are described in the ARM Debug Interface v5 Architecture Specification.
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