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Applies to: CoreSight
The CoreSight Architecture deliberately tries not to be prescriptive about what IO technology your chip must use. Generally it requires only that the signalling is single-ended in a supply range of 1.0V to 5.0V /- 10% and that signal changes can be detected around a common threshold indicated by Vtref. Please see the CoreSight v1.0 Architecture Specification:
especially sections 13.5 & 13.6.
Importantly, your signalling technology must be compatible with any restrictions of the Run Control (ICE) and Trace Port Analyzer (TPA) which you intend to be used with your system.
ARM's RealView ICE & Trace units again are adaptive to a wide range of supply voltages in the 1.0V to 5.0V /- 10% range.
The requirements for your output drives are simply that they can provide a detectable voltage swing around the reference threshold level when driving into a combined impedance of board wiring, connector and trace probe not exceeding 15pF. The frequency achievable will be a function of the quality of drivers used, such that your signal jitter plus skew does not exceed the trace probe's specified setup and hold margins within the data eye of the trace data; or to put it the other way, your SoC should be producing a trace clock frequency which is compatible with the ability of your trace port drivers to reliably center the trace clock edges in the data periods. The trace port analyzer will specify an upper limit on achievable trace frequency.
As the debug clock domain and the trace clock domain are decoupled from the functional clock domains inside the chip, there is no requirement to link debug and trace clock speeds to the operating speed of the device.
Both the CoreSight Spec and the RVI/RVT User Guide gives some useful advice on board design principles, termination, etc.
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