|ARM Technical Support Knowledge Articles|
Software or the debugger can inspect the Interrupt Program Status Register (IPSR).
Logic on-chip can use the ETMINTNUM[8:0] output bus to observe the corresponding value, if the ETM interface is enabled. This interface is available irrespective of whether the ETM is licensed and whether the ETM is instantiated in the configuration. The ETM interface is active when the TRCENA bit of the Debug Exception and Monitor Control Register (DEMCR) is set.
At RESET, the processor adopts Privileged Thread mode. The IPSR / ETMINTNUM is zero while the processor is in Thread mode (privileged or unprivileged), and changes to the corresponding exception number (ie. the vector table index) when an exception is being processed or handled.
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