ARM Technical Support Knowledge Articles

I-Cache, D-Cache and MMU combinations

Applies to: ARM926EJ-S

Scenario

There are three control bits in CP15 for ICache, DCache and MMU. What are the 'legal' combinations of these three bits?

Answer

Basically, the only prohibited combination of the three bits is when the
DCache is ON and the MMU is OFF. The table below shows all the possible
combinations of the three bits:


ICache | DCache | MMU | Allowed?
================================
Off    | Off    | Off | Yes
On     | Off    | Off | Yes
Off    | On     | Off | No
Off    | Off    | On  | Yes
On     | On     | Off | No
Off    | On     | On  | Yes
On     | Off    | On  | Yes
On     | On     | On  | Yes

There are two 'no', i.e. "not-allowed" settings for the
ICache/DCache/MMU combinations. These are both when the DCache is
enabled, but the MMU is disabled.

The above 'No' settings are allowed, in the sense that nothing bad will happen if
either of those particular combinations are chosen. It's just that with
the DCache enabled and the MMU disabled, the DCache will not work. The
following is a quote from the ARM926EJ-S TRM, for the situation where
the CP15 C1 C bit is set (controls enabling of the DCache) and the CP15
C1 M bit is clear (enables the MMU):

"1 0 DCache enabled, MMU disabled. The C bit is overriden by the M bit
setting, which means that the DCache is effectively disabled. All
data accesses are noncachable, nonbufferable, with no protection
checks. All addresses are flat mapped, that is VA = MVA = PA."

The above quote shows that while the "DCache ON, MMU OFF" combination is
legal, it will have no effect on the behaviour of the Data Cache.


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