ARM Technical Support Knowledge Articles

CODE BANKING LATCH ON EXTRA ADDRESS LINES

Applies to: C51 C Compiler

Answer

QUESTION

I am using Keil C51 Version 5.1 to develop a code banking application. I plan to use a 512Kx8 flash memory chip and I want to use 8 code banks. I plan to use the low 3 bits of port 1 to select the banks, connecting these 3 lines to the high three address pins of the FLASH.

The "8051 Utilities" manual is fairly clear on the coding and linking aspect, but I have a question about the hardware. The Four 64K Code Banks schematic shows a latch coming off ports 1 and 3, where the port 1.4 and 3.3 outputs are latched by the ALE line. My question is, do I need the latch? Is it OK to just connect the lines directly from port 1 to the EPROM chip ? I would think that the port 1 output pins are held in a stable state and no latching is required.

ANSWER

We have had mixed experiences with the bank switching hardware using port 1 or port 3 to select the upper address bits. There are a number of cases where using these lines direct from the CPU works. However, there are a few cases where they didn't. That is the reason for the latch.

Using the latch also guarantees that the lower address byte (P0) and the upper address bits are latched at the same time by ALE. The real answer to this is, if it works without the latch it works. However, the latch may be required in high-speed applications.

Using a 573 or 373 tied to ALE for the extra address lines causes ALL address lines (A8-A15 and your extra address lines) to be ready at the same time. This may not be a problem except in high-speed (24MHZ and faster) applications.

MORE INFORMATION

Article last edited on: 2006-10-23 17:35:07

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