ARM Technical Support Knowledge Articles

EXTS PROBLEMS USING THE _ATOMIC_ FUNCTION

Applies to: C166 C Compiler

Answer


Information in this article applies to:


SYMPTOMS

I have written the following code:

_atomic_(4);
Event = *ISREventPointer;
_atomic_(4);
*ISREventPointer = 0;

expecting interrupts to be disabled for the duration of the execution of both lines of C code. However, the assembly code generated was:

150E D130          ATOMIC    #04H
                                           ; SOURCE LINE # 1347
1510 DC0F          EXTS      R15,#01H
1512 A9AE          MOVB      RL5,[R14]
;---- Variable 'Event' assigned to Register 'RL5' ----
                                           ; SOURCE LINE # 1348
1514 D130          ATOMIC    #04H
                                           ; SOURCE LINE # 1349
1516 E10C          MOVB      RL6,#00H
1518 DC0F          EXTS      R15,#01H
151A B9CE          MOVB      [R14],RL6

If I am reading this correctly, the EXTS instruction will reset the internal counter being used for the ATOMIC instruction back to 1, causing only the following instruction (MOVB) to be non-interruptable.

Is there a workaround for this problem?

CAUSE

This happens because the EXTS instruction is required to execute the two lines of C code you have written. The result is that you run into a limitation of the microcontroller which cannot properly handle situations where EXTS instructions follow ATOMIC instructions.

RESOLUTION

There are two other methods to disable interrupts.

  1. Use #pragma DISABLE. This generates the necessary code to disable interrupts for the following function. For example:
    #pragma DISABLE
    
    void foo(void)
    {
      Event = *ISREventPointer;
      *ISREventPointer = 0;
    }
    
  2. Use the intrinsic _bfld_ function to achieve the same result as #pragma DISABLE, but for part of a function:
    _bfld_(PSW, 0xF000, 0xF000);     // disable interrupts
    _nop_();
    _nop_();
    Event = *ISREventPointer;
    *ISREventPointer = 0;
    _bfld_(PSW, 0xF000, 0x0000);     // enable interrupts
    

    Note the insertion of the two NOPs after the BFLD instruction. This is to avoid pipelining problems as it takes two instruction cycles for the interrupts to actually be disabled.

MORE INFORMATION

Article last edited on: 2005-07-15 13:12:33

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential