ARM Technical Support Knowledge Articles

ERRORS IN RTXCONF.A51 AND RTXSETUP.DCL

Applies to: RTX251 Real-time Kernel

Answer


Information in this article applies to:


SYMPTOMS

When I try to use the RTXCONF.A51 file and the RTXSETUP.DCL file from the TRAFFIC2, SAMPLE, or INTRPT examples in the C251RTX251 directory, I receive the following error messages when I assemble.

*** ERROR #45 IN 266 (RTXCONF.A51, LINE 83): UNDEFINED SYMBOL
*** ERROR #45 IN 274 (RTXCONF.A51, LINE 91): UNDEFINED SYMBOL
*** ERROR #45 IN 277 (RTXCONF.A51, LINE 94): UNDEFINED SYMBOL
*** ERROR #45 IN 280 (RTXCONF.A51, LINE 97): UNDEFINED SYMBOL
*** ERROR #45 IN 283 (RTXCONF.A51, LINE 100): UNDEFINED SYMBOL
*** ERROR #45 IN 283 (RTXCONF.A51, LINE 100): UNDEFINED SYMBOL
*** ERROR #45 IN 283 (RTXCONF.A51, LINE 100): UNDEFINED SYMBOL
*** ERROR #45 IN 286 (RTXCONF.A51, LINE 103): UNDEFINED SYMBOL
*** ERROR #45 IN 286 (RTXCONF.A51, LINE 103): UNDEFINED SYMBOL
*** ERROR #45 IN 287 (RTXCONF.A51, LINE 104): UNDEFINED SYMBOL
*** ERROR #45 IN 287 (RTXCONF.A51, LINE 104): UNDEFINED SYMBOL
*** ERROR #45 IN 288 (RTXCONF.A51, LINE 105): UNDEFINED SYMBOL
*** ERROR #45 IN 288 (RTXCONF.A51, LINE 105): UNDEFINED SYMBOL
*** ERROR #9 IN 413 (RTXCONF.A51, LINE 230): SYNTAX ERROR
*** ERROR #9 IN 413 (RTXCONF.A51, LINE 230): SYNTAX ERROR
*** ERROR #3 IN 413 (RTXCONF.A51, LINE 230): ILLEGAL CHARACTER
*** ERROR #3 IN 413 (RTXCONF.A51, LINE 230): ILLEGAL CHARACTER
*** ERROR #21 IN 429 (RTXCONF.A51, LINE 246): EXPRESSION WITH FORWARD REFERENCE NOT PERMITTED
*** ERROR #45 IN 429 (RTXCONF.A51, LINE 246): UNDEFINED SYMBOL
*** ERROR #9 IN 619 (RTXCONF.A51, LINE 436): SYNTAX ERROR

CAUSE

These error messages are caused by problems with these 2 files.

RESOLUTION

In RTXSETUP.DCL, change the CPU TYPE from:

;  1. CPU TYPE
;  ===========
;
;    CPU_TYPE stands for the desired microprocessor-type and can be
;    selected from the following table:
;
;  --------------------------------------------------------------------
;  | Manufacturer / Model                                   | 'xx'    |
;  --------------------------------------------------------------------
;  | Intel 8XC251SB                                         |   1     |
;  --------------------------------------------------------------------
;
?RTX_CPU_TYPE           EQU     9

to the following:

;  1. CPU TYPE
;  ===========
;
;    CPU_TYPE stands for the desired microprocessor-type and can be
;    selected from the following table:
;
;  --------------------------------------------------------------------
;  | Manufacturer / Model                                   | 'xx'    |
;  --------------------------------------------------------------------
;  | Intel 8XC251SB                                         |   1     |
;  --------------------------------------------------------------------
;
?RTX_CPU_TYPE           EQU     1

In RTXCONF.A51, remove the ?RTX_REENT_STKSIZE PUBLIC definition. Change the following:

PUBLIC  ?RTX_REENT_STKSIZE, ?RTX_STKSIZE

to this:

PUBLIC  ?RTX_STKSIZE

After your changes, these files should appear as follows:

RTXSETUP.DCL

;************************************************************************
;*                                                                      *
;*      R T X - 2 5 1   S E T U P                                       *
;*                                                                      *
;*----------------------------------------------------------------------*
;*                                                                      *
;*      Filename:       RTXSETUP.DCL                                    *
;*      Date:            8-MAY-1996                                     *
;*      Language:       Keil C (C251)                                   *
;*      Dev.system:     IBM PC (MS-WIN 95)                              *
;*      Targetsystem:   Any system based upon MCS-251                   *
;*                                                                      *
;*      Purpose:        Gives the user the possibility to configure RTX *
;*                      to meet his application specific requirements.  *
;*                                                                      *
;*                                  *** NOTE ***                        *
;*                                                                      *
;*                      - Read user manual carefully before changing    *
;*                        this file.                                    *
;*                      - This module may be used without any changes   *
;*                        for most applications !                       *
;*                      - This is an include file for RTXCONF.A51       *
;*                      - If any changes are done then RTXCONF.A51 has  *
;*                        to be rebuilt:                                *
;*                                              A251 RTXCONF.A51        *
;*                                                                      *
;*----------------------------------------------------------------------*
;* Rev. | Released | Programmer  | Comments                             *
;*----------------------------------------------------------------------*
;* 0.10 | 26.01.95 | EG          | Rel. 0.1 (BETA)                      *
;* 0.20 | 27.10.95 |             | Changes                              *
;* 0.30 |  4.03.96 |             | Replace ?RTX_INT251 by __INTR4__     *
;* 0.40 |  8.05.96 |             | Add ?RTX_USE_IDLE                    *
;* 2.10 | 30.07.97 |K. Birsen    | ?RTX_INTBASE will be always 0        *
;* 2.11 | 29.08.97 |K. Birsen    | RTX_REENT_STKSIZE is removed         *
;*      |          |             | has no meaning any more              *
;* 2.11 | 29.08.97 |K. Birsen    | ?RTX_INTBASE is removed              *
;*      |          |             | has no meaning any more              *
;*      |          |             |                                      *
;************************************************************************
;*  (c)  METTLER  &  FUCHS  AG,  CH-8953 Dietikon,  Tel. 01-740 41 00   *
;************************************************************************

;*----------------------------------------------------------------------*
;*                                                                      *
;*                         O V E R V I E W                              *
;*                                                                      *
;*      Configuration Options:                                          *
;*                                                                      *
;*              1. CPU TYPE                                             *
;*              2. SYSTEM CLOCK                                         *
;*              3. INITIAL INTERRUPT-ENABLE REGISTER VALUES             *
;*              4. TASK STACK SIZE                                      *
;*              5. ROUND-ROBIN FLAG                                     *
;*              6. MAILBOX-SUPPORT FLAG                                 *
;*              7. SEMAPHORE-SUPPORT FLAG                               *
;*              8. IDLE MODE                                            *
;*                                                                      *
;*      The configuration may be done directly by editing the include   *
;*      file RTXSETUP.DCL or (more easily) by using the intercative     *
;*      configuration program.                                          *
;*                                                                      *
;*----------------------------------------------------------------------*


;  1. CPU TYPE
;  ===========
;
;    CPU_TYPE stands for the desired microprocessor-type and can be
;    selected from the following table:
;
;  --------------------------------------------------------------------
;  | Manufacturer / Model                                   | 'xx'    |
;  --------------------------------------------------------------------
;  | Intel 8XC251SB                                         |   1     |
;  --------------------------------------------------------------------
;
?RTX_CPU_TYPE           EQU     1


;  2. SYSTEM CLOCK
;  ===============
;
;  (Basically Timer-0, Timer-1 and Timer-2 are supported)
;  Set ?RTX_SYSTEM_TIMER to 0 for Timer 0
;  Set ?RTX_SYSTEM_TIMER to 1 for Timer 1
;  Set ?RTX_SYSTEM_TIMER to 2 for Timer 2
;  (Default-value: Timer 0)
;
?RTX_SYSTEM_TIMER       EQU     0


;  3. INITIAL INTERRUPT-ENABLE REGISTER VALUES
;  ===========================================
;
;  Some MCS 251 family members have specific bits in their Interrupt-Enable
;  Registers, which have other functions than interrupt enable/disable.
;  Here you can set the initial values of these special bits.
;  (Normally RTX-251 will set all not used bits in the interrupt enable mask
;  to 0).
;  You MUST NOT set bits dedicated to interrupt enable/disable !
;  NOTE: ?RTX_IEN1_INIT is only used for processors with at least 2 interrupt
;        masks.
;       ?RTX_IEN2_INIT is only used for processors with 3 interrupt masks.
;
?RTX_IE_INIT            EQU     0
?RTX_IEN1_INIT          EQU     0
?RTX_IEN2_INIT          EQU     0


;  4. TASK STACK SIZE
;  ==================
;
;  This constant defines the maximum size of stack data (number of bytes).
;  For each defined task such an area is reserved in direct space.
;
;  The greatest possible task-stack size is limited by available EDATA
;  memory only.
;  (Default value: 64 Bytes)
;
?RTX_STKSIZE            EQU     64



;  5. ROUND-ROBIN FLAG
;  ===================
;
;  Optionally a time sharing dispatch scheme may be used for tasks with priority 0.
;
;  0 --> Do not use round-robin scheduling
;  1 --> Use round-robin scheduling
;  (Default value: 0)
;
?RTX_TIMESHARING        EQU     0




;  6. MAILBOX-SUPPORT FLAG
;  =======================
;
;  This flag determines if memory is allocated for the mailbox FIFOs or not.
;  If set to 0, then no wait for a mailbox is possible.  Associated calls
;  will return a NOT_OK in this case.
;  Set ?RTX_MAILBOX_SUPPORT to 0 if mailbox services are not desired.
;  Set ?RTX_MAILBOX_SUPPORT to 1 if mailbox services are desired.
;  (Default is 1)
;
?RTX_MAILBOX_SUPPORT    EQU     1


;  7. SEMAPHORE-SUPPORT FLAG
;  =========================
;
;  This flag determines if memory is allocated for the semaphore FIFOs or not.
;  If set to 0, then no wait for a semaphore is possible.  Associated calls
;  will return a NOT_OK in this case.
;  Set ?RTX_SEMAPHORE_SUPPORT to 0 if semaphore services are not desired.
;  Set ?RTX_SEMAPHORE_SUPPORT to 1 if semaphore services are desired.
;  (Default is 1)
;  NOTE: if an increased XDATA usage compared with RTX-51 V 4.x has to be
;         avoided, then this flag should be set to 0 !
;
?RTX_SEMAPHORE_SUPPORT  EQU     1


;  8. IDLE MODE
;  ============
;
;  If this option is enabled, then each time the RTX idle loop is
;  entered the cpu is switched to idle mode.
;
;  USE_IDLE        = 0: do not use the idle mode
;                  = 1: set cpu to idle mode during system idle time

?RTX_USE_IDLE             EQU     1


;*----------------------------------------------------------------------*
;*              END of INCLUDE FILE RTXSETUP.DCL                        *

RTXCONF.A51

$TITLE ('RTX-251 CONFIGURATION')
$SYMBOLS
$NOXREF
$NOCOND
$NOMOD51
$PAGELENGTH(80) PAGEWIDTH(110)
;************************************************************************
;*                                                                      *
;*    R T X - 2 5 1    Configuration data for RTX-251 V2.x              *
;*                                                                      *
;*----------------------------------------------------------------------*
;*                                                                      *
;*    Filename:        RTXCONF.A51                                      *
;*    Language:        Keil A251                                        *
;*    Dev. system:     IBM PC (MS-WIN 95)                               *
;*    Targetsystem:    Any system based upon intel MCS-251              *
;*                                                                      *
;*    Date:             9-MAY-1996                                      *
;*                                                                      *
;*    Purpose:         - Defines the processor specific data            *
;*                       definitions for all supported processors.      *
;*                       New processor types may be easily added.       *
;*                     - Defines all user configurable system values.   *
;*                                                                      *
;*----------------------------------------------------------------------*
;* Rev. |  Released   | Programmer    | Comments                        *
;*----------------------------------------------------------------------*
;* 0.00 |  12.10.94   | EG            | RTX-51 V 5.0 version            *
;* 0.10 |  26.01.95   |               | First modifications for RTX-251 *
;* 0.20 |  27.07.95   |               | Definitions for 8XC251SB        *
;* 0.21 |  11.08.95   |               | Introduce ?RTX_INT251           *
;* 0.30 |  18.12.95   |               | Enable cond. mbx/sem support    *
;* 0.31 |  25.01.96   |               | Comments                        *
;* 0.40 |   4.03.96   |               | Evaluate __INT4__ of DK251 V1.1 *
;* 0.50 |  22.04.96   |               | Add timer 2 support             *
;* 0.60 |   9.05.96   |               | Add ?RTX_IDLE_FUNC              *
;************************************************************************
;*    (c) METTLER  &  FUCHS  AG,  LOEWENSTRASSE 21,  CH-8953 Dietikon   *
;*    Tel. (+41) (1) 740 41 00  /  Fax  (+41) (1) 740 15 67             *
;************************************************************************

;*----------------------------------------------------------------------*
;*
;*  USER CONFIGURABLE SYSTEM VALUES
;*
;*  All configurable values are contained in include file RTXSETUP.DCL
;*  (for details see the program documentation).
;*----------------------------------------------------------------------*

$INCLUDE(RTXSETUP.DCL)

;========================================================================
;  END OF USER-CONFIGURABLE SECTION
;========================================================================


$EJECT
;************************************************************************
;*                                                                      *
;*  THE FOLLOWING SECTIONS MUST NORMALLY NOT BE ALTERED BY THE USER     *
;*  ---------------------------------------------------------------     *
;*                                                                      *
;************************************************************************

NAME  ?RTX?CONFIGURATION      ; Do NOT alter the module name !

;*----------------------------------------------------------------------*
;*  IMPORTS
;*----------------------------------------------------------------------*

EXTRN BIT    (?RTX_ENA_INT_REG1, ?RTX_ENA_INT_REG2)     ; from RTXDATA
EXTRN BIT    (?RTX_INTR)                                ; from RTXDATA
EXTRN CODE   (?RTX_SYSCLK_INTHNDLR)                     ; from RTXCLK
EXTRN CODE   (?RTX_INT_HANDLER)                         ; from RTXINT
EXTRN DATA   (?RTX_TMP1)                                ; from RTXDATA


;*----------------------------------------------------------------------*
;*  EXPORTS
;*----------------------------------------------------------------------*

; System constants
PUBLIC  ?RTX_STKSIZE
PUBLIC  ?RTX_TIMESHARING
PUBLIC  ?RTX_MAILBOX_SUPPORT, ?RTX_SEMAPHORE_SUPPORT

; Initial Interrupt mask values
PUBLIC  ?RTX_IE_INIT, ?RTX_IEN1_INIT, ?RTX_IEN2_INIT

; Enable the interrupt enable registers for the selected processor
PUBLIC  ?RTX_INIT_INT_REG_FLAGS

; Interrupt number to enable-mask table
PUBLIC  ?RTX_INT_TO_BIT_TABLE_BASE

; Greatest interrupt number
PUBLIC  ?RTX_MAX_INT_NBR

; Processor specific interrupt enable masks
PUBLIC  ?RTX_IE, ?RTX_IEN1, ?RTX_IEN2

; Interrupt mask variables
PUBLIC  ?RTX_NM_IE,  ?RTX_TSK_IE
PUBLIC  ?RTX_NM_IE1, ?RTX_TSK_IE1
PUBLIC  ?RTX_NM_IE2, ?RTX_TSK_IE2

; System Timer constants
PUBLIC  ?RTX_CLK_INT_NBR                       ; EQUATE
PUBLIC  ?RTX_TLOW, ?RTX_THIGH, ?RTX_TMOD       ; DATA
PUBLIC  ?RTX_TCON                              ; DATA
PUBLIC  ?RTX_TFLAG, ?RTX_TCONTROL              ; BIT
PUBLIC  ?RTX_TMOD_AND_MASK, ?RTX_TMOD_OR_MASK  ; EQUATES
PUBLIC  ?RTX_TCON_AND_MASK, ?RTX_TCON_OR_MASK  ; EQUATES

; Idle function
PUBLIC  ?RTX_IDLE_FUNC

; Code links for mailbox support
PUBLIC  ?RTX_HANDLE_ISR_SEND_MES_,?RTX_HANDLE_NF_CHECK_REQ_,?RTX_NFL_EVENT_

; Mailbox and semaphore FIFO space
PUBLIC  ?RTX_MBX_PAGE
PUBLIC  ?RTX_MBX_PAGE_END
PUBLIC  ?RTX_SEM_PAGE
PUBLIC  ?RTX_SEM_PAGE_END


;*----------------------------------------------------------------------*
;*  MACROS
;*----------------------------------------------------------------------*

; This MACRO generates an RTX-251 interrupt entry point.

INT_ENTRY       MACRO   NO
EXTRN XDATA (?RTX_INT&NO&_TID)
PUBLIC          INT&NO&_VECTOR
                CSEG AT(3+(&NO&*8))
INT&NO&_VECTOR: MOV     ?RTX_TMP1, A             ; Save A
                MOV     A, #LOW(?RTX_INT&NO&_TID); Set up ptr to int. TID
                LJMP    ?RTX_INT_HANDLER         ; Jump to general ISR
                ENDM


;*----------------------------------------------------------------------*
;*  PROCESSOR SPECIFIC DATA DEFINITIONS
;*----------------------------------------------------------------------*

IF (?RTX_CPU_TYPE = 1)
   ;***********
   ;* Type 1  *
   ;***********
      ;------------------------------------------------------------------
      ; Define the number and addresses of the interrupt enable registers
      ; 8XC251SB -> 1 interrupt enable register
      ; (Set the not used registers to the same address as ?RTX_IE)

      INT_EN_MASK_NUMBER   EQU 1
      ?RTX_IE              DATA  0A8H
      ?RTX_IEN1            DATA  0A8H  ; not used
      ?RTX_IEN2            DATA  0A8H  ; not used

      ;------------------------------------------------------------------
      ; Generate the interrupt entry points supported by the peripherals
      ; of the selected CPU type.
      IF (?RTX_SYSTEM_TIMER = 0)
         ; Do NOT include the Timer 0 Vector  (INT-1)
         INT_ENTRY      0
         INT_ENTRY      2
         INT_ENTRY      3
         INT_ENTRY      4
         INT_ENTRY      5
         INT_ENTRY      6
      ELSEIF (?RTX_SYSTEM_TIMER = 1)
         ; Do NOT include the Timer 1 Vector  (INT-3)
         INT_ENTRY      0
         INT_ENTRY      1
         INT_ENTRY      2
         INT_ENTRY      4
         INT_ENTRY      5
         INT_ENTRY      6
      ELSEIF (?RTX_SYSTEM_TIMER = 2)
         ; Do NOT include the Timer 2 Vector  (INT-5)
         INT_ENTRY      0
         INT_ENTRY      1
         INT_ENTRY      2
         INT_ENTRY      3
         INT_ENTRY      4
         INT_ENTRY      6
      ENDIF

      ;------------------------------------------------------------------
      ; The following table attaches the interrupt numbers (0..31) to the
      ; corresponding bits in the interrupt enable masks of the specific
      ; processor.
      ; All three interrupt enable register contents must be defined
      ; for every interrupt number (even when the specific processor contains
      ; only one interrupt mask).
      ; Syntax: DB IE-content, IE1-content, IE2-content
      ;
      ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF  SEGMENT  CODE
                        RSEG  ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF

         ?RTX_INT_TO_BIT_TABLE_BASE:
                        DB 01H, 00H, 00H    ; INT_0  EX0 (INT0)
                        DB 02H, 00H, 00H    ; INT_1  ET0 (Timer 0)
                        DB 04H, 00H, 00H    ; INT_2  EX1 (INT1)
                        DB 08H, 00H, 00H    ; INT_3  ET1 (Timer 1)
                        DB 10H, 00H, 00H    ; INT_4  ES  (Ser. channel)
                        DB 20H, 00H, 00H    ; INT_5  ET2 (Timer 2)
                        DB 40H, 00H, 00H    ; INT_6  EC  (PCA)

      ;------------------------------------------------------------------
      ; Define the greatest supported interrupt number
      ?RTX_MAX_INT_NBR      EQU   6

PCON    DATA    87H

ENTER_IDLE       MACRO
;;
;;      Enter Idle Mode
;;      ---------------
;;      To be used whenever entering idle state.
;;
            ORL     PCON, #01H          ; Set idle mode (leave by interrupt)
            ORL     PCON, #20H          ; (peripherals stay active)
         ENDM

$ELSE

   THIS ?RTX_CPU_TYPE VALUE IS NOT SUPPORTED BY THIS MODULE !!

$ENDIF



$EJECT
;*----------------------------------------------------------------------*
;*  DEFINITIONS COMMON FOR ALL PROCESSORS
;*----------------------------------------------------------------------*

      ;------------------------------------------------------------------
      ; Define the internal interrupt mask variables. The variables are
      ; used for the Interrupt-Handling.
      ; Initialise the enable bits for the Interrupt-Enable-Masks
      ;
      IF (INT_EN_MASK_NUMBER = 1)
         ?RTX?INT_MASK?RTXCONF  SEGMENT  DATA
                                RSEG  ?RTX?INT_MASK?RTXCONF
            ; variables for first mask
            ?RTX_NM_IE:     DS 1
            ?RTX_TSK_IE:    DS 1
            ; variables for second mask (not used)
            ?RTX_NM_IE1:    DS 0
            ?RTX_TSK_IE1:   DS 0
            ; variables for third mask (not used)
            ?RTX_NM_IE2:    DS 0
            ?RTX_TSK_IE2:   DS 0

            ; RTX-251 calls this routine in the initialisation phase
            ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF  SEGMENT  CODE
                                    RSEG  ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
               ?RTX_INIT_INT_REG_FLAGS:
                                    CLR   ?RTX_ENA_INT_REG1
                                    CLR   ?RTX_ENA_INT_REG2
             $IF (__INTR4__ = 1)
                                    SETB  ?RTX_INTR
             $ELSE
                                    CLR   ?RTX_INTR
             $ENDIF
                                    RET
      ELSEIF (INT_EN_MASK_NUMBER = 2)
         ?RTX?INT_MASK?RTXCONF  SEGMENT  DATA
                                RSEG  ?RTX?INT_MASK?RTXCONF
            ; variables for first mask
            ?RTX_NM_IE:     DS 1
            ?RTX_TSK_IE:    DS 1
            ; variables for second mask
            ?RTX_NM_IE1:    DS 1
            ?RTX_TSK_IE1:   DS 1
            ; variables for third mask (not used)
            ?RTX_NM_IE2:    DS 0
            ?RTX_TSK_IE2:   DS 0

            ; RTX-251 calls this routine in the initialisation phase
            ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF  SEGMENT  CODE
                                    RSEG  ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
               ?RTX_INIT_INT_REG_FLAGS:
                                    SETB  ?RTX_ENA_INT_REG1
                                    CLR   ?RTX_ENA_INT_REG2
             $IF (__INTR4__ = 1)
                                    SETB  ?RTX_INTR
             $ELSE
                                    CLR   ?RTX_INTR
             $ENDIF
                                    RET
      ELSEIF (INT_EN_MASK_NUMBER = 3)
         ?RTX?INT_MASK?RTXCONF  SEGMENT  DATA
                                RSEG  ?RTX?INT_MASK?RTXCONF
            ; variables for first mask
            ?RTX_NM_IE:     DS 1
            ?RTX_TSK_IE:    DS 1
            ; variables for second mask
            ?RTX_NM_IE1:    DS 1
            ?RTX_TSK_IE1:   DS 1
            ; variables for third mask
            ?RTX_NM_IE2:    DS 1
            ?RTX_TSK_IE2:   DS 1

            ; RTX-251 calls this routine in the initialisation phase
            ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF  SEGMENT  CODE
                                    RSEG  ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
               ?RTX_INIT_INT_REG_FLAGS:
                                    SETB  ?RTX_ENA_INT_REG1
                                    SETB  ?RTX_ENA_INT_REG2
             $IF (__INTR4__ = 1)
                                    SETB  ?RTX_INTR
             $ELSE
                                    CLR   ?RTX_INTR
             $ENDIF
                                    RET
      ENDIF


      ;------------------------------------------------------------------
      ; Define the System-Timer specific values
      ; This values are normally for all 8051 family-members identical.
      ;
      IF (?RTX_SYSTEM_TIMER = 0)
         ?RTX_TLOW          DATA  8AH
         ?RTX_THIGH         DATA  8CH
         ?RTX_TCON          DATA  88H
         ?RTX_TMOD          DATA  89H
         ?RTX_TFLAG         BIT   8DH
         ?RTX_TCONTROL      BIT   8CH
         ; TCON init-masks
         ; The clock will be initialized with: ANL TCON, #RTX_TCON_AND_MASK
         ;                                     ORL TCON, #RTX_TCON_OR_MASK
         ; --> not used for this timer
         ?RTX_TCON_AND_MASK EQU   0FFH
         ?RTX_TCON_OR_MASK  EQU   000H
         ; TMOD init-masks
         ; The clock will be initialized with : ANL TMOD, #RTX_TMOD_AND_MASK
         ;                                      ORL TMOD, #RTX_TMOD_OR_MASK
         ?RTX_TMOD_AND_MASK EQU   0F0H
         ?RTX_TMOD_OR_MASK  EQU   01H
         ; System-Clock interrupt number
         ?RTX_CLK_INT_NBR   EQU   1
      ELSEIF (?RTX_SYSTEM_TIMER = 1)
         ?RTX_TLOW          DATA  8BH
         ?RTX_THIGH         DATA  8DH
         ?RTX_TCON          DATA  88H
         ?RTX_TMOD          DATA  89H
         ?RTX_TFLAG         BIT   8FH
         ?RTX_TCONTROL      BIT   8EH
         ; TCON init-masks
         ; The clock will be initialized with: ANL TCON, #RTX_TCON_AND_MASK
         ;                                     ORL TCON, #RTX_TCON_OR_MASK
         ; --> not used for this timer
         ?RTX_TCON_AND_MASK EQU   0FFH
         ?RTX_TCON_OR_MASK  EQU   000H
         ; TMOD init-masks
         ; The clock will be initialized with : ANL TMOD, #RTX_TMOD_AND_MASK
         ;                                      ORL TMOD, #RTX_TMOD_OR_MASK
         ?RTX_TMOD_AND_MASK EQU   0FH
         ?RTX_TMOD_OR_MASK  EQU   10H
         ; Interrupt Vector Entry
         ?RTX_CLK_INT_NBR   EQU   3
      ELSEIF (?RTX_SYSTEM_TIMER = 2)
         ?RTX_TLOW          DATA  0CCH  ; TL2
         ?RTX_THIGH         DATA  0CDH  ; TH2
         ?RTX_TCON          DATA  0C8H  ; T2CON
         ?RTX_TMOD          DATA  0C9H  ; T2MOD
         ?RTX_TFLAG         BIT   0CFH  ; TF2 (T2CON.7)
         ?RTX_TCONTROL      BIT   0CAH  ; TR2 (T2CON.2)
         ; TCON init-masks
         ; The clock will be initialized with: ANL TCON, #RTX_TCON_AND_MASK
         ;                                     ORL TCON, #RTX_TCON_OR_MASK
         ?RTX_TCON_AND_MASK EQU   000H  ; T2CON = 000H
         ?RTX_TCON_OR_MASK  EQU   000H
         ; TMOD init-masks
         ; The clock will be initialized with: ANL TMOD, #RTX_TMOD_AND_MASK
         ;                                     ORL TMOD, #RTX_TMOD_OR_MASK
         ?RTX_TMOD_AND_MASK EQU   000H  ; T2MOD = 000H
         ?RTX_TMOD_OR_MASK  EQU   000H
         ; Interrupt Vector Entry
         ?RTX_CLK_INT_NBR   EQU   5
      ENDIF

      ;------------------------------------------------------------------
      ; System-Timer Interrupt Vector Entry
      ;
      CSEG AT(3+(8*?RTX_CLK_INT_NBR))
      IF (?RTX_SYSTEM_TIMER = 2)
         CLR   ?RTX_TFLAG
      ENDIF
         LJMP  ?RTX_SYSCLK_INTHNDLR

      ;------------------------------------------------------------------
      ;
      ; Enable mailbox support code links
      ;
        ?RTX?RTX_MBX?RTXCONF  SEGMENT  CODE
                              RSEG  ?RTX?RTX_MBX?RTXCONF
IF (?RTX_MAILBOX_SUPPORT = 1)
EXTRN CODE   (?RTX_HANDLE_ISR_SEND_MES)                 ; from RTXIHNDM
EXTRN CODE   (?RTX_HANDLE_NF_CHECK_REQ)                 ; from RTXIHNDM
EXTRN CODE   (?RTX_NFL_EVENT)                           ; from RTXSNDM

?RTX_HANDLE_ISR_SEND_MES_:
        LJMP    ?RTX_HANDLE_ISR_SEND_MES
?RTX_HANDLE_NF_CHECK_REQ_:
        LJMP    ?RTX_HANDLE_NF_CHECK_REQ
?RTX_NFL_EVENT_:
        LJMP    ?RTX_NFL_EVENT
ELSE
?RTX_HANDLE_ISR_SEND_MES_:
        RET
?RTX_HANDLE_NF_CHECK_REQ_:
        RET
?RTX_NFL_EVENT_:
        ERET
ENDIF


      ;------------------------------------------------------------------
      ;
      ; RTX Idle Function
      ;
      ; RTX-251 jumps to this code when entering the idle loop

        ?RTX?RTX_IDLE_FUNC?RTXCONF SEGMENT  CODE
                                    RSEG  ?RTX?RTX_IDLE_FUNC?RTXCONF
        ?RTX_IDLE_FUNC:
IF (?RTX_USE_IDLE = 1)
                ; Switch to idle mode when configured
                ENTER_IDLE
ENDIF

Article last edited on: 2000-03-12 00:00:00

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