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DEBUGGING WITH THE NMI (NON-MASKABLE INTERRUPT)

Applies to: RTX251 Real-time Kernel

Answer


Information in this article applies to:


QUESTION

In the readme.txt file for RTX251, there is an indication that the NMI interrupt on the Temic devices is supported.

Debugging with Monitor-251 on Keil MCB-251

...In addition to the above interrupts, Keil MCB-251 uses the NMI vector of the Temic 251 derivatives and the TRAP interrupt vector. To work with RTX-251 you must therefore modify the RTXCONF.A51 file and comment out the interrupt vector generation for INT0, SIO INT and NMI INT.

However, upon examination of the CONF file, there is no support for the NMI interrupt (INT-7).

;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
      IF (?RTX_SYSTEM_TIMER = 0)
         ; Do NOT include the Timer 0 Vector  (INT-1)
         INT_ENTRY      0
         INT_ENTRY      2
         INT_ENTRY      3
         INT_ENTRY      4
         INT_ENTRY      5
         INT_ENTRY      6
      ELSEIF (?RTX_SYSTEM_TIMER = 1)
.
.
.
         ?RTX_INT_TO_BIT_TABLE_BASE:
                        DB 01H, 00H, 00H    ; INT_0  EX0 (INT0)
                        DB 02H, 00H, 00H    ; INT_1  ET0 (Timer 0)
                        DB 04H, 00H, 00H    ; INT_2  EX1 (INT1)
                        DB 08H, 00H, 00H    ; INT_3  ET1 (Timer 1)
                        DB 10H, 00H, 00H    ; INT_4  ES  (Ser. channel)
                        DB 20H, 00H, 00H    ; INT_5  ET2 (Timer 2)
                        DB 40H, 00H, 00H    ; INT_6  EC  (PCA)
.
.
.
;------------------------------------------------------------------
; Define the greatest supported interrupt number
      ?RTX_MAX_INT_NBR      EQU   6

Is there a version of RTX251 that supports the NMI interrupt and the Temic chips?

ANSWER

RTX251 does not support NMI. So, no, there is no version of RTX251 that supports the NMI on the Temic chips.

SEE ALSO

Article last edited on: 2000-03-30 00:00:00

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