ARM Technical Support Knowledge Articles
PL351 NAND Flash Memory Controller Knowledge Articles
Knowledge Articles in this section
Can we use PL351 low power mode using APB control even if AXI interface low-power signals are tied to inactive level (csysreq=1, cclken=0)?
Does PL351 IP support simultaneous program/erase operation with multi-plane NAND devices?
Does PL351 supports RANDOM PAGE READ commands when in NAND boot mode?
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