ARM Technical Support Knowledge Articles
ARM920/922T Knowledge Articles
Knowledge Articles in this section
Bus Interface (4)
Cache and Write Buffer (3)
Reset and Initialization (3)
Are the IRQ and FIQ interrupts level-sensitive?
Are there are any special considerations when memory mapping hardware registers?
Do I need to keep the clock running when the reset line is asserted?
During AMBA test some signals toggle unpredictably. Why is this?
How can the ARM banked registers be initialized?
How do I add scan chains to the ARM TAP controller?
How do I lockdown part of my data cache?
How does Little / Big Endian mode affect aligned / unaligned addressing?
I'm not implementing an external coprocessor. How should I tie off the interface?
If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
In which direction do the debug scan chains scan?
Is there a priority scheme for exceptions?
Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
What are the considerations when designing with an ARM hard macro clock?
What are the timing requirements of interrupts entering the ARM core?
What do I set the ARM TAP IDCODE to?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens inside the ARM core when an exception occurs?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the timing relationship between TDI/SDIN and TDO/SDOUTBS?
What values are in ARM registers after a power-on reset?
Which cached cores are available and what do they include?
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