ARM Technical Support Knowledge Articles
Cortex-M4 Knowledge Articles
Knowledge Articles in this section
Bus Interface (7)
Accessing 64-bit peripherals using Cortex-M processors
Bit-banded accesses versus read-modify-write accesses
Can Cortex-M3 / Cortex-M4 make a simultaneous instruction fetch and data access to Code space?
Can Cortex-M3/4 have a pending Halt after Reset?
Can Cortex-M4 interrupt the Lazy Stacking operation?
Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
Can I set the MPU to prevent any further modification of the MPU settings?
Can I use 16-bit memory for Thumb-2 code?
Can I use both SWO Single Wire Output and the Parallel Trace Port for trace?
Can a Cortex-M3/M4 check the contents of the ETM by reading the TPIU Integration Registers?
Does Cortex-M3 or Cortex-M4 provide status information to distinguish between cold and warm reset?
Does my Cortex-M3 or Cortex-M4 processor support Multi-drop Serial Wire Debug?
How are Memory Type and Memory Attributes represented on the AHB-Lite bus interfaces of Cortex-M3 and Cortex-M4?
How can I count the number of instructions executed by the processor in a given time interval?
How can I enable the ETM interface signals of Cortex-M4 or Cortex-M4?
How can I ensure that WFE causes sleep?
How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?
How can a Cortex-M processor wake up from WFI if interrupts are masked or disabled?
How can software identify one Cortex-M3/4 processor instance in a SoC containing multiple instances?
How do I boot a Cortex-M3 or Cortex-M4 processor with uninitialized memory at address zero?
How do I get the best performance when compiling floating point code for Cortex-M4F?
How do I run the "fpu" validation test in my RTL simulation?
How does Cortex-M3 and Cortex-M4 conform to the ARMv7-M Architecture for Load and Store Exclusives?
How does the DMIPS/MHz performance vary with wait-states on the code memory?
How flexible is the interrupt and excpetion priority scheme in ARMv7-M?
How to access a Cortex-M processor's memory system from my own Debug transactor?
I cannot find the "Integration and Implementation Manual" (IIM) on infocenter.arm.com
IIM description of HMASTERD = 0b10 does not make sense
Is there a simple way to measure the execution performance of arbitrary code in simulation?
My test for memory Bus Fault gets stuck repeating the fault again and again
Serial Wire Debug sequence fails to produce WAIT responses for wait-states then generates WDATAERR
The ARMv7-M ARM describes address 0xE000E000 as the SCS, but the TRM and IIM describe it as the NVIC. Which is it?
Unable to access TPIU registers, they appear to be stuck at zero
Unable to program the Data Watchpoint Unit / Data Watchpoint and Trace Unit (DWT)
Unexpected memory behavior at addresse ranges 0x22xxxxxx, 0x23xxxxxx, 0x42xxxxxx or 0x43xxxxxx
What AHB-Lite burst lengths are produced by Cortex-M3 and Cortex-M4?
What are STCALIB and STCLKEN or STCLK, and how should I connect them in the SoC?
What is CTIINTISR[1:0]?
What is the behavior when an exception occurs while executing a floating operation?
What is the depth of the ITM FIFO?
What is the difference between DAPEN and DBGEN?
What is the effect of DAPABORT?
What is the format of the Cortex-M4 tarmac.log file?
What is the true interrupt latency of Cortex-M3 and Cortex-M4 for interrupt entry and exit?
Which AHB-Lite BURST and TRANSFER types are produced by Cortex-M3 and Cortex-M4?
Why does my Cortex-M processor Lock Up with a Hard Fault a few cycles after reset?
Why is the SysTick Calibration TENMS value one less than the number of clock cycles required for 10ms?
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