ARM Technical Support Knowledge Articles
Cortex-M4 Knowledge Articles
Knowledge Articles in this section
Bus Interface (3)
Can Cortex-M3/4 have a pending Halt after Reset?
Can Cortex-M4 interrupt the Lazy Stacking operation?
Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
Can I set the MPU to prevent any further modification of the MPU settings?
Can I use 16-bit memory for Thumb-2 code?
Can a Cortex-M3/M4 check the contents of the ETM by reading the TPIU Integration Registers?
Does Cortex-M3 or Cortex-M4 provide status information to distinguish between cold and warm reset?
How are Memory Type and Memory Attributes represented on the AHB-Lite bus interfaces of Cortex-M3 and Cortex-M4?
How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?
How can a Cortex-M processor wake up from WFI if interrupts are masked or disabled?
How do I boot an ARMv7-M processor with uninitialized memory at address zero?
How do I get the best performance when compiling floating point code for Cortex-M4F?
How does Cortex-M3 and Cortex-M4 conform to the ARMv7-M Architecture for Load and Store Exclusives?
How flexible is the interrupt and excpetion priority scheme in ARMv7-M?
I cannot find the "Integration and Implementation Manual" (IIM) on infocenter.arm.com
My test for memory Bus Fault gets stuck repeating the fault again and again
What are STCALIB and STCLKEN or STCLK, and how should I connect them in the SoC?
What is the behavior when an exception occurs while executing a floating operation?
What is the difference between DAPEN and DBGEN?
What is the effect of DAPABORT?
Why does my Cortex-M processor Lock Up with a Hard Fault a few cycles after reset?
Why is the SysTick Calibration TENMS value one less than the number of clock cycles required for 10ms?
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