ARM Technical Support Knowledge Articles
PL341 AXI DDRII Dynamic Memory Controller Knowledge Articles
Knowledge Articles in this section
Can I connect my own DDR PHY with ARM PL34X DDR Memory controllers or is it restricted only to ARM Artisan DDR PHY?
Can I individually set refresh periods for each connected memory chip?
Is the row boundary crossing possible in case of WRAP bursts ?
Is there a restriction between aclk and mclk in asynchronous mode?
What is the maximum AXI burst length in PL341? How is this affected by the FIFO depths?
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