ARM Technical Support Knowledge Articles
ARM926EJ-S Knowledge Articles
Knowledge Articles in this section
Bus Interface (9)
Cache and Write Buffer (5)
Reset and Initialization (4)
Are the IRQ and FIQ interrupts level-sensitive?
Are there are any special considerations when memory mapping hardware registers?
Can I increase the number of processes allowed by the Fast Context Switch Extensions?
Can I use my ARM926 code for an ARM11 core ?
Can I use the ARM926 with a single-layer AHB system?
Can we supply the RTL of the ARM cores to our customer or EDA vendors?
Do I need to implement byte-write access on the ITCM?
Do I need to keep the clock running when the reset line is asserted?
Does the ARM926 support RETRY response from a slave?
How can I generate LOCKed, Exclusive and burst transfers on ARM926 and ARM1176 cores?
How can the ARM banked registers be initialized?
How can the ARM926EJ-S perform overlapped transfers
How do I generate an imprecise abort on the ARM926EJS as part of a test case?
I'm not implementing an external coprocessor. How should I tie off the interface?
I-Cache, D-Cache and MMU combinations
If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
Is RTCK required as a dedicated output?
Is a DesignWare foundation license required to synthesize the ARM synthesizable cores?
Is it possible to configure the ARM9 core to more than 2 hardware breakpoints or watchpoints?
Is there a priority scheme for exceptions?
Question regarding address translation with ARM926EJ-S
Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
What AHB bus burst types are used by the ARM926EJ-S?
What AHB transactions will my ARM core generate?
What are the differences between the AHB Interfaces of the ARM9E family cores?
What are the main differences between ARM926EJ-S and ARM946E-S?
What are the metal layer constraints for LF072-ARM926EJ-SMIC 013G design kit ?
What cache sizes can be used in the ARM926EJ-S Macrocell?
What combinations of INITRAM and VINITHI will allow booting from ITCM?
What do I set the ARM TAP IDCODE to?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens inside the ARM core when an exception occurs?
What is the Endianness of the core after reset?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the state of the MMU at reset?
What is the state of the caches at reset?
What is the test strategy for ARM soft cores?
What values are in ARM registers after a power-on reset?
When does the ARM926EJ-S use its Write Buffer?
Where can I find the DSP instruction set of the ARM926EJ-S?
Where will the ITCM be located at reset?
Which cached cores are available and what do they include?
Why does my ARM926EJ-S run slowly compared with an ARM7TDMI?
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